The cathode ray tube (CRT) has been around as a display device for many years. Its considerable bulk makes the CRT inconvenient to use, and it has long been a goal to replace it by more convenient flat screen technology. Field-emission displays (FEDs) have shown considerable promise as a flat screen, but they suffer from a problem of low luminance, which makes them impractical to use in situations where there is a high ambient light.
FEDs employ a phosphor screen similar to tile one employed in a CRT. Instead of using a deflected beam from a single electron gun to energize the phosphors, FEDs employ an array of micro field-emitters in close proximity to the screen and all integrated on the same emitting assembly facing the anode. Pixels are defined as elementary points of the anode. The VGA standard, defined by IBM and used in many computer displays, has 480 rows and 640 columns of pixels.
In CRTs and FEDs alike, phosphor and the viewer's eye remanance make pixels appear as continuously bright even though they are bombarded by an electron beam only a small portion of the time. The luminosity of a pixel is proportional to the time during which it is illuminated by an electron beam and to its intensity.
Any color can be obtained as a combination of red, blue and green. Color images in FEDs, as in CRTs, are formed by illuminating red, blue and green sub-pixels independently; the eye blends the three different colors and sees the resulting color only. A sub-pixel is defined as one of the three color components of a pixel: each pixel has at least one red, one blue and one green sub-pixel. Each color corresponds to a different phosphor material. The three types of phosphors can be deposited periodically on the screen in parallel stripes. To keep the same resolution of images as in a monochrome screen, the red, green and blue stripes each have a width of one third of the width of a pixel.
Low luminance is still a problem FEDs have to overcome before they can be used in high ambient lights. A lot of effort is being put towards synthesizing new phosphors with a higher luminous efficiency at low anode voltages [Vecht, Chakovskoi]. The other natural approach is to increase the power delivered to the anode. Integrated focusing structures [Kesling] have been proposed to reduce the typical 15 to 30.degree. half-aperture angle of the beams emitted by the cathode. This allows increasing the anode to cathode distance without losing resolution, and consequently increasing the anode voltage without breakdown. The best solution to keep a relatively high density of emitters is to deposit a second insulating layer and a second gate on top of the extraction gate, with a wider aperture [Py, Itoh]. The second gate, called the focus gate, is biased at a lower voltage than the first one to repel marginal rays. The power delivered to each pixel can be further enhanced by increasing the current.
FIG. 1 shows a typical field-emitter used in FEDs. A microtip 1 made of a suitable emitting material is deposited on a metallic or semi-conducting cathodic layer 100 surrounded by an insulator layer 2 on which a conductive or semi-conductive layer 3, called the extraction gate, is fabricated. Layers 2 and 3 have an aperture over the microtip 1 so that the microtip is exposed to vacuum. Microtip 1, and layers 100, 2 and 3 are deposited on a same substrate (not shown) and form the emitting assembly.
Electrons are extracted from the microtip 1 when a high field is produced at its apex by positively biasing the extraction gate 3 with respect to the microtip 1. The voltage of the microtip 1 is applied through layer 100. The electric field makes the Fermi barrier so thin that electrons can tunnel through, as described by Fowler and Nordheim [R. H. Fowler and L. W. Nordheim, Proc. Roy. Soc. A119, 173 (1928)]. The extracted electrons are emitted into vacuum and follow paths described by Newton's laws of motion and by the electrostatic laws.
A fabrication technique for field emitters is disclosed in U.S. Pat. No. 3,789,471, C. A. Spindt K. R.Shoulders L. N. Heynick and in the article by C. A. Spindt, J.Appl. Phys, vol 39 (1968) p3504. Micro-electronic techniques permit the integration of micron-size tips with extraction gates so close that a fraction of a micro-ampere can be obtained for an extraction gate to microtip voltage less than 100V.
The emission current as a function of that voltage has a diode-like characteristic. For the purposes of the following discussion, it will be assumed that microtips emit at a voltage of 80V (except when a second gate, described as the focusing/deflection gate in the statement of invention, is biased at a high negative voltage), and do not emit when this voltage is reduced to 50V. As shown in FIG. 1, light is obtained by illuminating a phosphor anode 6 with an electron beam from the underlying micro-emitter 1.
Electron field emitters in FEDs are addressed in a XY matrix fashion, as described for example in U.S. Pat. No. 4,857,799 to C. A. Spindt and C. E. Holland. The image is formed by turning on or off the emitters facing each pixel. This eliminates the need for beam-rastering and gives FEDs their flat display characteristics.
As shown in FIG. 2, the FEDs consist of a grid having rows 301, 302, 303 and columns 101, 102, 103. The rows are formed of conductive or semiconductive material containing apertures forming the extraction gates, which are arranged in groups. The columns are formed strips of conductive or semiconductive material supporting the microtips also arranged in groups and in positions corresponding to the groups of apertures formed in the rows. The groups of microtips and corresponding extraction gates lie at the intersections of the rows and columns and define cells, each of which lies under a pixel, such as 601, 603. The designation of rows and columns is arbitrary, and it is not necessary that they be arranged in an orthogonal manner.
As shown in FIG. 3a, the emitting assembly is addressed gate row by gate row, and the pixels of the anode are illuminated pixel row by pixel row, a pixel row being defined as a group of pixels arranged in a parallel fashion to the gate rows. The active gate row 302 is biased at +50V, while all the others are at 0V. Cells at the intersection of that gate row and columns 101 and 103 biased at -30V emit electrons towards pixels 601 and 603. All other cells have an extraction gate to microtip voltage difference of 50V, 30V or 0V and do not emit electrons. For the same image frequency, gate row by gate row addressing enables a much longer illumination time for each pixel than the pixel by pixel addressing mode of a CRT. For example, in a VGA FED, each pixel can be illuminated 1/480 of the time rather than 1/(480*640) in a VGA CRT.
FIGS. 3b and c are top view of FEDs in the two color addressing modes. In each Figure, the gray gate row is the active one (biased at +50V), whereas other gate rows are grounded. The emitting cells are the intersections of those rows and columns biased at -30V.
In the switched cathode mode of FIG. 3b, the columns addressing the microtips are separated in three smaller columns, hereinafter referred to as sub-columns, and the phosphor stripes are parallel to the columns. A sub-cell is defined as the intersection of a gate row and a sub-column. The three sub-pixels of the same pixel can be illuminated at the same time since they are illuminated by sub-cells of the same row. Thus, the time of illumination of a sub-pixel is the same as the time of illumination of a pixel in a monochrome FED. If the red, green and blue phosphors have the same luminous efficiency as phosphors used in monochrome displays, the addressing mode would have the same luminance as a monochrome FED. The emitting assembly is addressed gate row by gate row and the anode is illuminated pixel row by pixel row. The gray row is the addressed row so that electrons can be emitted from their intersection with selected sub-columns. Gate row 312 is biased at +50V and sub-columns 111, 112, 114 and 116 are biased at -30V simultaneously, so sub-cells at the intersection of gate row 312 and those columns emit electrons and sub-pixels 611, 612, 614 and 616 are illuminated. All other sub-cells do not emit.
The phosphor stripes could also be parallel to the rows, but then sub-pixels could not be illuminated simultaneously so the luminance of the screen would be three times lower.
In the switched anode mode shown in FIG. 3c, the emitting assembly is the same as in a monochrome display for a same pixel resolution. In order to address each sub-pixel of a same pixel independently, each color stripe of the anode is electrically separated and illuminated sequentially. Color stripes can be arranged parallel to the columns as in FIG. 3c or parallel to the rows as in FIG. 3d. The color image is formed by sequential formation of the red, green, and blue images. In FIG. 3c, when the red image is formed, the red stripes 721, 724 and 727 on the anode are biased at a high voltage whereas green stripes 722, 725 and 728 and blue stripes 723, 726 and 729 are biased at -30V so that electrons cannot reach them.
In FIG. 3d, when the red image is formed, the red stripes 733, 736 and 739 on the anode are biased at a high voltage whereas green stripes 732, 735 and 738 and blue stripes 731, 734 and 737 are biased at -30V so that electrons cannot reach them. In both cases, all the red stripes are grouped together, as are the green and blue stripes respectively. The inter-digital system formed is switched only three times during an image formation because the red, green and blue images are formed sequentially.
The emitting assembly is addressed in a gate row by gate row manner, so the anode is still illuminated in a pixel row by pixel row manner, even though only one of the three colors of a pixel is illuminated at a time. The gray row 322 is biased at +50V and columns 121 and 122 are biased at -30V, so the cells at the intersection of gate row 322 and those columns emit.
In FIG. 3c, the electrons are directed towards red sub-pixels 621 and 622 which, being part of stripes 722 and 725, are biased at +200V. In FIG. 3d, the electrons are directed towards red sub-pixels 631 and 632 which, being part of stripe 736, are biased at +200V.
The advantage of switched anode mode when compared to a monochrome display is that only three connections are necessary for the anode rather than one, but no extra connections are necessary for the cathode. By comparison, the number of column connections in the switched cathode mode is increased by a factor of three. In the switched anode mode, the current received by a sub-pixel is the same as the current received by a pixel in a monochrome screen. Assuming that red, green and blue phosphors have the same luminous efficiency as phosphors used in monochrome displays, this means that this addressing mode would have the same luminance as a monochrome FED.
One disadvantage of the switched anode addressing mode is illustrated in FIG. 4. This simulation corresponds to the case of FIG. 3d, but the worst case also applies to the case of FIG. 3c. As seen in FIG. 4, a significantly portion of the electrons emitted by the cell at the intersection of gate row 332 and column 131 actually do not reach the sub-pixel 631 but are repelled by neighboring sub-pixels. The current received by the sub-pixel, and the luminosity of the screen, is thus decreased. Lost electrons can reach a sub-pixel of the same color in another pixel and create cross-talk or might return to the extraction gate and damage it.
Beams emitted by microtips have a typical 15 to 30 degree half-angle aperture. Thus, for a given resolution of the screen, the distance from anode to emitting assembly is limited, which in turn limits the anode voltage under the breakdown limit. For this reason, FEDs use phosphors at much lower voltage than cathode ray tubes. Phosphors have a low luminous efficiency at the low anode voltages used in FEDs. Thus the luminance of FEDs can be enhanced by reducing the aperture of the beams emitted by microtips because then the anode to cathode distance can be increased which permits using a higher anode voltage. This can be achieved by integrating focusing electrodes on the cathode in a known fashion [W. D. Kesling and C. E. Hunt, IEEE Trans ED 42(2) p 193-200 (1995)]. In FIG. 5, a microtip 1 made of any emitting material is fabricated on a metallic or semi-conducting layer 100 surrounded by an insulator layer 2 on which a conductive or semi-conductive layer 3 is deposited. On top of extraction gate 3, a second insulating layer 4 and a second gate 5, hereafter referred to as a focus gate, are added. Focus gate 5 can be made of any metallic or semi-conductive material. Insulating layer 4 and focus gate 5 have openings substantially facing the opening in extraction gate 3 and insulating layer 2. Focus gate 5 is biased at a lower voltage than extraction gate 2 so that marginal rays are repelled towards the normal to the plane of the cathode, and the aperture of the beam is significantly reduced.
A. Hoeberechts G. VanGorkom introduced the concept of integrating deflection electrodes to an emitting assembly [EP0184868 A. Hoeberechts G. VanGorkom]. One or several electrodes, made of a conductive or semi-conductive material, are integrated substantially in the same plane as the extraction gate and electrically disconnected from it. These electrodes are referred to as deflection gates. In FIG. 6, microtips 1 are fabricated on a metallic or semi-conductive layer 100 and surrounded by an insulator 2 and an extraction gate 342. On each side of extraction gate 342, two electrodes 341 and 343, hereafter referred to as deflection gate, are fabricated substantially in the same plane as extraction gate 342. By biasing the left deflecting gate 341 at a voltage lower than that of the extraction gate 342 and the right deflection gate 343 at a voltage higher than that of the extraction gate 342, the beam emitted by the microtips of the row is deflected towards the right side of anode 6.
An object of the invention is to enhance the luminance of field emission displays.